Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

First 7 nm EUV Chip Tapes Out at TSMC

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC’s second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML’s Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

While the advantages of N7+ over its predecessors are not significant (e.g., TSMC has never mentioned performance increases that the new tech is expected to bring), it will still almost certainly be embraced wholeheartedly by developers of mobile SoCs who need to release new chips every year. That said, it is not surprising that TSMC has already taped out the first chip using its N7+ technology. Furthermore, the company is prepping a specialized version of N7 process aimed at the automotive industry, which indicates that N7/N7+ is going to be a “long” node.

TSMC is not disclosing the name of the customer whose N7+ SoC it has taped out, but considering the foundry’s alpha customers for new process technologies in the recent years, the leading suspects are obvious.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10% 20%
Performance 40% 20% 30% ? same (?) 15%
Area Reduction none >50% 70% >37% ~17% 45%

5 nm on Track

After N7+ comes TSMC’s first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC’s N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

EDA tools for the N5 node will be ready in November, so chip designs may be well underway now. But while many foundation IP blocks for N5 are ready today, there are important missing pieces, such as PCIe Gen 4 and USB 3.1 PHYs, which may not be ready until June. For some of TSMC's clients the lack of these pieces is not a problem, but many will have to wait.

One of the factors that prevents smaller companies from designing FinFET chips is development cost. Some estimates put the average cost to develop an SoC at around $150 million in labor and IP licenses. With N5 generation, these expenditures will rise to $200 – $250 million, according to EETAsia, which will limit the number of parties interested in using the tech.

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Source: EETAsia

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  • RU482 - Wednesday, October 10, 2018 - link

    Lithography fanboy-ism is an interesting phenomenon. Lots of apples and oranges.
    Intel certainly does seem to be more confused/distracted than ever. Their marketing, channel support, and product line is frankly all over the place.
    Get it together Intel!
  • Anymoore - Wednesday, October 10, 2018 - link

    5nm uses multipatterning with EUV: look under item (4)
  • IJD - Wednesday, October 10, 2018 - link

    No, N5 EUV is single-patterned. The colouring is not because of multi-patterning, it's because of the 3:2 pitch ratio between poly (underlying cell) and metal (interconnect), so there are 4 different versions of each cell depending on how they fit on the metal grid and what cell is next to them -- the metal position walks past the poly, and this also depends on the width of the cell. The tools use colouring to sort all this out.
  • Anymoore - Wednesday, October 10, 2018 - link

    That's not what coloring is for. "the M1 layer requires (full) multipatterning color assignment"
  • IJD - Wednesday, October 10, 2018 - link

    Yes, but not because of multiple EUV exposures, it's because of the mismatched metal/poly pitch. 5nm definitely uses single-exposure EUV on all layers.
  • Anymoore - Wednesday, October 10, 2018 - link

    Did you miss the word "multipatterning"? Single exposure uses no coloring. Color doesn't cross layers.
  • r3loaded - Wednesday, October 10, 2018 - link

    Please could you clarify what is meant by "risk production" in the context of chip manufacturing (yes, I've already googled it). Does it mean they're putting real chip designs through the production process as a sort of pipe cleaner?
  • name99 - Wednesday, October 10, 2018 - link

    More useful is to consider the gap between when "risk production" is announced and we see a large volume of chips commercially available.

    TSMC 7nm started risk production in April 2017, and we see volume shipments 17 months later.
    10nm was about the same.
    16nm risk production started Nov 2013, Apple chips were almost 2 years later.

    Of course there are issues of schedule alignment and the need to build up a huge stockpile of chips before any company (let alone Apple) can release a product. But judging by history it seems possible that Apple can pick up 7+ in 2019. It would be tight, but assuming the ONLY real changes are the EUV, and that's under control (which may be optimistic...)

    5N is more interesting. I had assumed (before I looked at the historical numbers) that this would mean Apple in 2020, with early iPad chips perhaps in Q2 2020. That still seems possible, within the historical bounds (the A10X was released about 14 months after risk 10nm production) but both schedules seem tight, especially if 5nm has a lot of new features.
    My guess is Apple will still make the iPhone deadline, but an early iPad chip in 2020 might be too much to expect?
  • quadibloc - Sunday, October 14, 2018 - link

    If TSMC is the first to successfully use EUV in routine production, before Intel, this indeed will be a major milestone. I've been very reluctant to conclude that Intel has fallen behind because of its apparent 10 nm issues, but now it appears that there may be substance to it. However, there are also recent Intel announcements that imply that 10 nm is now back on track as well.
  • IJD - Friday, October 19, 2018 - link

    Both TSMC and Samsung will have EUV in limited use on 7nm+ nodes with production next year, but with EUV only on ~5 layers, mainly for contacts/vias where a pellicle isn't essential. Both are targeting full-EUV for 5nm the year after (2020). Intel are nowhere with EUV because they've been running round like chickens with their heads chopped off trying (and failing) to fix 10nm.

    The recent Intel announcements about 10nm are papering over the cracks -- yes they're working on improving things, yes they're still aiming to have IceLake (for laptops) out in late 2019, but the process won't be good enough to yield big server chips until late 2020, which is 18 months after AMD Rome and four years after when this was initially forecast.

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