5nm
Synopsys has introduced the industry's first full-stack AI-powered suite of electronic design automation tools that covers all stages of chip design, from architecture to design and implementation to manufacturing. The Synopsys.ai suite promises to radically reduce development time, lower costs, improve yields, and enhance performance. The set of tools is set to be extremely useful for chips set to be made on leading-edge nodes, such as 5nm, 3nm, 2nm-class, and beyond. Chip Design Challenges As chips gain complexity and adopt newer process technologies, their design and manufacturing costs escalate to unprecedented levels. Designing a reasonably complex 7 nm chip costs about $300 million (including ~ 40% for software). In contrast, the design cost of an advanced 5 nm processor exceeds $540 million (including software), according to...
TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
TSMC this week has said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The...
33 by Anton Shilov on 4/5/2019
ASML to Ship 30 EUV Scanners in 2019: Faster EUV Tools Coming
ASML said last week that it planned to ship 30 extreme ultraviolet scanners in 2019, up significantly from 2018. The plan is not surprising, as demand for EUV lithography...
17 by Anton Shilov on 1/28/2019
TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its...
50 by Anton Shilov on 10/9/2018
Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019
Samsung recently hosted its Samsung Foundry Forum 2018 in Japan, where it made several significant foundry announcements. Besides reiterating plans to start high-volume manufacturing (HVM) using extreme ultraviolet lithography...
29 by Anton Shilov on 9/6/2018
Arm and Samsung Extend Artisan POP IP Collaboration to 7LPP and 5LPE Nodes
Arm and Samsung Foundry this week announced plans to extend their collaboration to 7LPP and 5LPE process technologies. Under the terms of the agreement, Arm will offer Samsung Foundry...
23 by Anton Shilov on 7/6/2018
GlobalFoundries Gives 7 nm Capacity Update, Mulls Skipping 5 nm
High-ranking executives of GlobalFoundries this month gave several updates concerning future plans of the contract maker of semiconductors. As it appears, in a bid to provide more tangible advantages...
19 by Anton Shilov on 5/31/2018
Samsung Foundry Roadmap: EUV-Based 7LPP for 2018, 3 nm Incoming
Samsung Foundry this week updated its fabrication technology roadmap, introducing a number of changes and announcing the first details about its 3 nm manufacturing process that is several years...
25 by Anton Shilov on 5/24/2018
TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the...
10 by Anton Shilov on 5/8/2018
TSMC Kicks Off Volume Production of 7nm Chips
TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it...
63 by Anton Shilov on 4/24/2018
Change of Strategy: A New GlobalFoundries CEO in Dr. Thomas Caulfield
In a surprising move, GlobalFoundries has announced that its CEO is stepping down. Sanjay Jha, who lead the world’s second largest foundry for four years, was in the past...
15 by Anton Shilov on 3/15/2018
TSMC Starts to Build Fab 18: 5 nm, Volume Production in Early 2020
TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC’s 5 nm process starting from early 2020...
27 by Anton Shilov on 1/31/2018
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