SK Hynix Develops First 16 Gb DDR5-5200 Memory Chip, Demos DDR5 RDIMM
by Anton Shilov on November 15, 2018 7:00 AM EST
SK Hynix on Thursday announced that it had completed development of its first DDR5 memory chip. The new chip offers a capacity of 16 Gb and is said to be the industry’s first DRAM that is fully compliant with the JEDEC standard, which is yet to be published. Meanwhile, mass production of SK Hynix's DDR5 memory chips is slated for 2020.
The new DDR5 chip from SK Hynix supports a 5200 MT/sec/pin data transfer rate, which is 60% faster than the 3200 MT/s rate officially supported by DDR4. Meanwhile the DRAM operates at 1.1 Volts, a 9% decrease in operating voltage. The monolithic 16 Gb chip is made using SK Hynix’s second generation 10 nm-class process technology (also known as 1Ynm), though the company does not disclose its die size and other peculiarities.
Looking forward, SK Hynix expects its DDR5 lineup to include DRAM chips at 8 Gb, 16 Gb, and 32 Gb capacities, with data transfer rates ranging from 3200 to 6400 MT/s.
Besides announcing the memory chip, SK Hynix also demonstrated the industry’s first DDR5 Registered DIMM. The DDR5-5200 RDIMM module offers a peak memory bandwidth of 41.6 GB/s, which is in line with DDR4 modules overclocked to their extremes (using LN2-cooled CPUs, etc.). The DDR5 RDIMM itself features 288 pins on a slightly curved edge connector (to reduce the insertion force on every pin), yet its layout and design are a bit different when compared to DDR4 to avoid insertion of DDR5 modules into DDR4 slots and vice versa.
SK Hynix said that it had already shipped DDR5 RDIMMs and UDIMMs to a “major chipset maker” (Intel?) to assist in the development of server and client platforms supporting the new type of memory.
SK Hynix intends to start mass production of DDR5 memory sometimes in 2020, when the aforementioned platforms (at least one of them) are expected to hit the market.
Overall, JEDEC expects DDR5 to bring in I/O speeds ranging from 4266 to 6400 MT/s, with a supply voltage drop to 1.1 V and an allowable fluctuation range of 3% (i.e., at ±0.033V). Along with the performance improvements, the new memory standard also stands to improve in total capacity and DIMM density, with chips planned for 16Gb and beyond.
Under the hood, the new standard will will also bring several major enhancements to the design of memory modules, with the goal of improving their real-world performance and enabling higher data transfer rates. For example, each DDR5 DIMM will feature two independent 32/40-bit channels (without/or with ECC). Furthermore, DDR5 will have a better command bus efficiency (as the channels will have their own 7-bit Address (Add)/Command (Cmd) buses), better refresh schemes, and an increased bank group for extra performance.
Last month Cadence said that enhanced functionality of the standard will enable DDR5 to offer a 36% higher real-world bandwidth vs. DDR4 at the same data transfer rate. While we will not be able to test this claim before 2020, the improvements of DDR5 compared to the predecessor certainly look impressive.
Related Reading:
- Cadence & Micron DDR5 Update: 16 Gb Chips on Track for 2019
- Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019
- JEDEC: DDR5 to Double Bandwidth Over DDR4, NVDIMM-P Specification Due Next Year
Source: SK Hynix
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DanNeely - Thursday, November 15, 2018 - link
I'm a bit puzzled. Looking at that I see what appear to be 10 dram chips and 1 something else on the dimm. Normally you'd expect to see 8/16 or 9/18 dram chips depending on if it's ECC or not; and only server ram would have an additional chip as a buffer (to let them put more dimms on the bus). The DDR5 micron demoed (related reading) has a normal looking 8 dram chips; so I'm wondering what's the deal with this Dimm's unusual appearance.rpg1966 - Thursday, November 15, 2018 - link
Is it related to "each DDR5 DIMM will feature two independent 32/40-bit channels (without/or with ECC)"?That is, do you need two sets of (4+1) instead of one set of (8+1) memory chips to support ECC with two channels? I have no idea, but I was wondering the same thing.
DanNeely - Thursday, November 15, 2018 - link
That's a plausible theory anyway. And since the article says it's a registered (server class) dimm, it presumably is ECC. Doubling the BoM level ECC tax isn't good, but trying to play games to share a single ECC chip with 2 independent channels would probably have a significant performance impact.Cpt.Planet - Thursday, November 15, 2018 - link
There are 10 DRAM ICs and a RCD. 4+1 ECC per channel. The chip in the middle is the RCD (registered clock driver) for RDIMM.5080 - Thursday, November 15, 2018 - link
I assume that DDR5 will also need a new chipset and probably a new socket. AMD's Zen 2 and 3 will still be on AM4. This pretty much rules out DDR5 support for Zen 2 and 3. So the earliest we can see DDR5 support is 2021 with Zen 4. At that time we probably also get an updated PCI-Express bus either v.4 or v.5.AAbattery - Thursday, November 15, 2018 - link
With AMD's chiplet design, the microarchitecture of Zen 2 and 3 can be developed independently of the I/O chip that contains the memory controller, therefore all that's needed is a new platform and I/O chip, and Zen 2 could support DDR5, though they will definitely wait until Zen 3 since that will be ready by the time DDR5 is mass produced.While they could wait until Zen 4, I doubt they will.
namechamps - Thursday, November 15, 2018 - link
AMD has said Zen 2 will use the AM4 socket. That pretty much precludes it from using DDR5. Zen 3 on the other hand may move to a new socket.namechamps - Thursday, November 15, 2018 - link
Correction from another anad article Zen 3 will use the same sockets as well. So Zen 4 is the earliest."IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides?
MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.
IC: So one might assume that an intercept might occur with Zen 4?
MP: No comment (!)"
Alexvrb - Thursday, November 15, 2018 - link
Support for a socket does not preclude support for that socket plus another socket. Although, this would still mean Zen 3 at the earliest.porcupineLTD - Thursday, November 15, 2018 - link
"We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change."~Mark Papermasterso no DDR5 until at least Zen 4.