Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

First 7 nm EUV Chip Tapes Out at TSMC

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC’s second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML’s Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

While the advantages of N7+ over its predecessors are not significant (e.g., TSMC has never mentioned performance increases that the new tech is expected to bring), it will still almost certainly be embraced wholeheartedly by developers of mobile SoCs who need to release new chips every year. That said, it is not surprising that TSMC has already taped out the first chip using its N7+ technology. Furthermore, the company is prepping a specialized version of N7 process aimed at the automotive industry, which indicates that N7/N7+ is going to be a “long” node.

TSMC is not disclosing the name of the customer whose N7+ SoC it has taped out, but considering the foundry’s alpha customers for new process technologies in the recent years, the leading suspects are obvious.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
Power 60% 40% 60% <40% 10% 20%
Performance 40% 20% 30% ? same (?) 15%
Area Reduction none >50% 70% >37% ~17% 45%

5 nm on Track

After N7+ comes TSMC’s first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC’s N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

EDA tools for the N5 node will be ready in November, so chip designs may be well underway now. But while many foundation IP blocks for N5 are ready today, there are important missing pieces, such as PCIe Gen 4 and USB 3.1 PHYs, which may not be ready until June. For some of TSMC's clients the lack of these pieces is not a problem, but many will have to wait.

One of the factors that prevents smaller companies from designing FinFET chips is development cost. Some estimates put the average cost to develop an SoC at around $150 million in labor and IP licenses. With N5 generation, these expenditures will rise to $200 – $250 million, according to EETAsia, which will limit the number of parties interested in using the tech.

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Source: EETAsia

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  • WatcherCK - Tuesday, October 9, 2018 - link

    Intel is a "too big to fail" company that can appeal to the power of that white house and its occupants if it really came to that...
  • HighTech4US - Tuesday, October 9, 2018 - link

  • aj7 - Wednesday, October 10, 2018 - link

    Really? What’s their whine line?
  • .vodka - Tuesday, October 9, 2018 - link

    Intel has already lost their historical ~3 year manufacturing advantage. Their 10nm process is similar to TSMC's 7nm which is already shipping and pumping out working silicon (Apple's A12, AMD's Epyc Rome/Zen2, etc).

    We'll see what Icelake is capable of when it is released and how well Intel's revised and relaxed 10nm process (original 10nm has been scrapped AFAIK) works.

    The i3 8121u in 10nm the first is a disaster of epic proportions (70mm² dual core chip with completely disabled iGPU and worse clocks/TDP than similar 14++ parts) that has not been reviewed at all, anywhere. It only shipped in an obscure Lenovo laptop just to claim 10nm is working and avoiding lawsuits.
  • brakdoo - Tuesday, October 9, 2018 - link

    Intel is already doing "risk production" with 10 nm but yeah, Intels 10 nm will compete against 7FF+ and at least for a short period against 5FF until Intel goes EUV with 7 nm...

    Judging by the big number of EUV machines sold to Intel, TSMC and Samsung none of these will have a big advantage once real EUV( more than one layer) comes into play.
  • Santoval - Wednesday, October 10, 2018 - link

    According to a June '18 article at SemiWiki Intel plans to be just as aggressive when they move to 7nm - which I believe is still scheduled for a... 2020 release on their roadmap, which surely requires an update. They plan a further 2.4x increase in transistor density, i.e. about ~250 MTr/mm^2. That density is much higher than TSMC's and Samsung's expected transistor density at 5nm, and it is even slightly higher than TSMC's and Samsung's projected transistor density at 3nm.

    What I mean is that Intel still plans to shoot way too far, as if they learnt nothing from the overambitious specs of their 10nm node which resulted in repeated delays. Due to the huge jump in density SemiWiki expects that there is no way they can go so small with FinFet, so they predict a switch to HNS (Horizontal Nanosheets, a form of GAA - Gate All Around). Perhaps HNS, along with EUV on almost the entire stack, will help them achieve this. But even if they do there is no way they manage to do it before 2022 at the earliest, 2023 more realistically.

    By that time Samsung and TSMC will have long deployed 5nm, which is going to be much denser than Intel's 10nm (TSMC's anyway, Samsung's is expected to be only slightly denser) and they will either be on the verge of mass releasing 3nm or they will have already released it, depending on how much Intel's 7nm node is delayed and the potential delays of the foundries.

    Intel was already left behind the foundries due to the delay of 10nm and TSMC's release of 7nm (the same applied to Intel's 14nm vs the foundries' 10nm, but to a lesser degree), will probably match them for a few quarters when they release 10nm based CPUs in late 2019, and they will again be left behind from around mid 2020 (when TSMC plans to release 5nm in high volume) until 2022 (i.e. 2023), when Intel releases their 7nm node in high volume.

    All the above only assume a "quantitative" lead in transistor density, and ignore more complex qualitative metrics like LER (line edge rounghness), transistor materials, leakage, power efficiency etc etc Intel might still lead in some (or all) of these aspects.
  • t_oven - Wednesday, October 10, 2018 - link

    TSMC is at 7nm while Intel still at 14nm now, so they already lost in term of process node. Why do you need to wait for 5nm?
  • Wilco1 - Wednesday, October 10, 2018 - link

    Indeed. Intel lost its lead years ago - TSMC 10nm was already much denser than Intel 14nm.
  • JKflipflop98 - Saturday, October 13, 2018 - link

    Don't worry about good ol' Intel.
    You're gonna be blown away with what's coming out of their pipe.
  • Stochastic - Tuesday, October 9, 2018 - link

    Is it safe to assume that 7FF+ will form the foundation for next-gen consoles?

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